1. Field of the Invention
The present disclosure relates to a method of fabricating a semiconductor device employing selectivity poly deposition. More particularly, the present disclosure relates to a method of fabricating a high-integration semiconductor device that may reduce or minimize contact surface resistance resulting from a salicide process by employing selectivity poly deposition in forming a CMOS transistor in the semiconductor device.
2. Background of the Related Art
Referring to FIG. 1 and FIG. 2, a conventional method of fabricating a semiconductor device is illustrated. FIG. 1 shows a flow chart of one conventional method of fabricating a semiconductor device. FIG. 2 schematically illustrates, in a cross-sectional view, a semiconductor device according to the conventional method of fabricating a semiconductor device outlined in FIG. 1.
In accordance with the conventional method of fabricating a semiconductor device, a Shallow Trench Isolation structure (hereinafter referred to as “STI”) 11 is formed over a semiconductor substrate.
A gate oxide layer is grown on the substrate in regions other than the location of the STI 11 (S102), and a polysilicon layer is deposited (S103) on the gate oxide layer. Thereafter, a patterning process is performed (S104) to form a gate poly 2 over a gate oxide 1. A low concentration of dopant ions are implanted into the silicon substrate (S105) to form lightly doped source/drain regions, as is known in the art.
Spacers 3 are formed on the sidewalls of the gate poly (S106). In addition, a high concentration of dopant ions for forming the source/drain regions are implanted (S107).
However, in the above-mentioned conventional process for fabricating a semiconductor device, one of the largest problems in a logic and analog device is the increased surface resistance of poly salicide. When the semiconductor device is minimized in order to form a high-integration circuit, and as the high-integration circuit requires a great miniaturization for gate electrodes and source/drain regions, a problem arises that the surface resistance of the gate poly increases due to the decrease of the semiconductor device in size.
U.S. Pat. No. 4,610,078, Matsukawa et al., discloses a method of manufacturing a semiconductor device in which the margin for the semiconductor wafer at the step of forming the contact hole is reduced, thereby increasing the packing density of elements in semiconductor wafer.
U.S. Pat. No. 5,006,911, Richard D. Sivan, discloses a transistor device having a gate centered in an active region in which the gate does not extend beyond the active region.
U.S. Pat. No. 6,080,661, Subhas Bothra, discloses methods for making reliable conductive vias in semiconductor devices that are fabricated over a semiconductor wafer by fabricating conductive contacts down to diffusion regions and transistor gates in self-aligned contact processes.